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ADV7195
CLOCK
t 9
t 10
R0
R1
R2
Rxxx
Rxxx
PIXEL INPUT
DATA
G0
B0
G1
B1
G2
B2
G3
B3
Gxxx
Bxxx
Gxxx
Bxxx
t 11
t 12
t 9 - CLOCK HIGH TIME
t 10 - CLOCK LOW TIME
t 11 - DATA SETUP TIME
t 12 - DATA HOLD TIME
Figure 1. 4:4:4 RGB Input Data Format Timing Diagram
CLOCK
t 9
t 10
Y0
Y1
Y2
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0
Cr0
Cb1
Cr1
Cbxxx
Crxxx
t 11
t 12
t 9 - CLOCK HIGH TIME
t 10 - CLOCK LOW TIME
t 11 - DATA SETUP TIME
t 12 - DATA HOLD TIME
Figure 2. 4:2:2 Input Data Format Timing Diagram
CLOCK
t 9
t 10
Y0
Y1
Y2
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cbxxx
Crxxx
Cbxxx
Crxxx
t 11
t 12
t 9 - CLOCK HIGH TIME
t 10 - CLOCK LOW TIME
t 11 - DATA SETUP TIME
t 12 - DATA HOLD TIME
Figure 3. 4:4:4 YCrCb Input Data Format Timing Diagram
–6 –
REV. A
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